Title :
Receiver front-end chipsets for 2.4-GHz wireless LAN in 0.5 μm BiCMOS
Author :
Wuen, Wen-Shen ; Liu, Shen-Fong ; Chen, Kuang-Yu ; Wen, Kuei-Ann
Author_Institution :
Inst. of Electron., Nat. Chiao Tung Univ., Hsinchu, Taiwan
fDate :
11/1/1999 12:00:00 AM
Abstract :
The paper presents the design and implementation of receiver front-end chipsets for 2.4-GHz 802.11 Wireless LAN. The chipsets consist of low noise amplifier and down conversion mixers in single-balanced and double-balanced structures. The LNA is designed with optimum bias technique for minimizing noise figure. The front-end chipsets are fabricated with 0.5-μm BiCMOS process with fT of 13-GHz and packaged in SOP8 package. It is presented that under 802.11 standard specified system link budget, the chipset hit the design performance and leave the design margin of 4.89 dB
Keywords :
BiCMOS integrated circuits; UHF integrated circuits; radio receivers; wireless LAN; 0.5 micron; 2.4 GHz; BiCMOS chipset; SOP8 package; bias technique; double-balanced mixer; down conversion mixer; low noise amplifier; low-power design; noise figure; receiver front-end; single-balanced mixer; wireless LAN; 1f noise; BiCMOS integrated circuits; CMOS technology; Circuit noise; GSM; Impedance; Inductors; Noise figure; Packaging; Wireless LAN;
Conference_Titel :
Microwave Conference, 1999 Asia Pacific
Print_ISBN :
0-7803-5761-2
DOI :
10.1109/APMC.1999.829905
