DocumentCode
1722042
Title
Separation of intrinsic and parasitic MOSFET parameters using a multiple built-in Kelvin test structure
Author
Kasai, Naoki ; Mori, Hidemitsu ; Matsuki, Takeo ; Yamamoto, Ichiro ; Koyama, Kuniaki
Author_Institution
ULSI Device Dev. Lab., NEC Corp., Sagamihara, Japan
fYear
1997
Firstpage
198
Lastpage
202
Abstract
A new MOSFET test structure built in multiple Kelvin patterns is used to evaluate scaled-down MOSFET characteristics through separation of intrinsic and parasitic parameters. Transistor characteristics and contact resistance of individual MOSFETs are simultaneously measured to clarify the direct correlation between fluctuation of MOSFET characteristics and that of parasitic contact resistance. MOSFET performance without parasitic interconnect resistance can be also measured to define intrinsic current drivability in a MOSFET fully scaled-down to less than sub-half-micrometers dimensions
Keywords
MOSFET; contact resistance; semiconductor device testing; MOSFET; contact resistance; current drivability; fluctuations; interconnect resistance; intrinsic parameters; multiple built-in Kelvin test structure; parasitic parameters; scaled-down characteristics; sub-half-micrometer technology; Contact resistance; Electric resistance; Electric variables measurement; Electrical resistance measurement; Fluctuations; Kelvin; MOSFET circuits; Plugs; Testing; Wiring;
fLanguage
English
Publisher
ieee
Conference_Titel
Microelectronic Test Structures, 1997. ICMTS 1997. Proceedings. IEEE International Conference on
Conference_Location
Monterey, CA
Print_ISBN
0-7803-3243-1
Type
conf
DOI
10.1109/ICMTS.1997.589396
Filename
589396
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