Title :
A scalable synchronous system
Author :
Afghahi, M. ; Svensson, C.
Author_Institution :
LSI Design Center, Linkoping Univ., Sweden
Abstract :
The performance of the synchronous timing scheme for VLSI-based systems is examined. It is shown that traditional clocking used in this scheme leads to serious performance shortcoming, particularly for submicrometer technologies. A novel mode of clocking is proposed and examined in detail. This clocking mode makes the performance of the synchronous system almost scalable with scaling the feature size of MOS devices. The application of this mode of clocking to H-tree networks, usually used in systolic arrays, is also investigated.<>
Keywords :
MOS integrated circuits; VLSI; clocks; H-tree networks; MOS devices; VLSI-based systems; clocking mode; scalable synchronous system; synchronous timing scheme; systolic arrays; traditional clocking; Clocks; Delay estimation; Delay lines; Integrated circuit interconnections; Inverters; Large scale integration; Performance analysis; Propagation delay; Timing; Very large scale integration;
Conference_Titel :
Circuits and Systems, 1988., IEEE International Symposium on
Conference_Location :
Espoo, Finland
DOI :
10.1109/ISCAS.1988.14966
