FPGA-implementation of pipelined neural network for power amplifier modeling

FPGA-Implementation of pipelined real-valued time-delay neural network (RVTDNN) for power amplifier modeling is presented in this paper. Pipelined and pseudo-conventional RVTDNN architectures are implemented on their parallel forms to exploit the inherent concurrent computing tasks of field programmable gate array (FPGA). The proposed pipelined architecture is based on the delayed back-propagation learning algorithm for adaptive correction of neuron weights and biases. The proposed pipelined RVTDNN has a reduced critical path and an increased maximum operating frequency to 6.5 times faster than pseudo-conventional RVTDNN. Results obtained with both RVTDNN models using a modulated 16-QAM baseband signal are very close to those obtained comparing with the reference model.