Statistical delay modelling of manufacturing process variations at system level

Process variation has become a major issue in system performance estimation as the technology feature size continues to decrease. This paper proposes a statistical methodology to bring the process variation effects from transistor level up to system level in terms of circuit delay. A cell library has been built which offers a rapid analysis of process variation effects on system delay performance. As a demonstration vehicle for this technique, the delay distribution of a micropipeline circuit has been simulated using this cell library. The experimental results show that the proposed method is much faster than the traditional SSTA approach by a factor of 50; the results are also compared with Monte Carlo simulation data for validation purposes, and show an acceptable error rate of within 5% and in most cases less than 3%.