Title :
Three Subthreshold Flip-Flop Cells Characterized in 90 nm and 65 nm CMOS Technology
Author :
Alstad, Håvard Pedersen ; Aunet, Snorre
Author_Institution :
Dept. of Inf., Univ. of Oslo, Oslo
Abstract :
This paper examines three different flip-flop designs in subthreshold operation. All flip-flops are simulated in a 65 nm and 90 nm process with a supply voltage ranging from 125 mV to 1V. Process variations are examined at different process corners. Successful operations of a PowerPC 603 flip-flop at all process corners with a supply voltage down to 125 mV is shown at 65 nm. The best PDP and EDP numbers of flip-flops design at VDD = 200 mV in this paper are 53.6 aJ and 0.88 yJs, respectively.
Keywords :
CMOS integrated circuits; flip-flops; integrated circuit design; CMOS technology; PowerPC 603 flip-flop; flip-flops design; size 65 nm; size 90 nm; subthreshold flip-flop cells; supply voltage; voltage 125 mV to 1000 mV; Application software; CMOS technology; Circuits; Energy consumption; Flip-flops; Informatics; Leakage current; Power dissipation; Power supplies; Threshold voltage;
Conference_Titel :
Design and Diagnostics of Electronic Circuits and Systems, 2008. DDECS 2008. 11th IEEE Workshop on
Conference_Location :
Bratislava
Print_ISBN :
978-1-4244-2276-0
Electronic_ISBN :
978-1-4244-2277-7
DOI :
10.1109/DDECS.2008.4538745
