DocumentCode
1723061
Title
Incremental SAT Instance Generation for SAT-based ATPG
Author
Tille, Daniel ; Drechsler, Rolf
Author_Institution
Inst. of Comput. Sci., Univ. of Bremen, Bremen
fYear
2008
Firstpage
1
Lastpage
6
Abstract
Due to ever increasing design sizes more efficient tools for automatic test pattern generation (ATPG) are needed. Recently ATPG based on Boolean satisfiability (SAT) has been shown to be a beneficial complement to traditional ATPG techniques. This paper makes two contributions. Firstly, we analyze the two steps SAT-based ATPG consists of with respect to their run time on industrial benchmarks. Secondly, exploiting these analysis results, we propose an incremental solving technique with the objective to speed up the entire classification process. An experimental evaluation of the proposed method shows a significant reduction of the overall run time of the SAT- based ATPG process.
Keywords
automatic test pattern generation; design for testability; Boolean satisfiability; SAT-based ATPG; automatic test pattern generation; incremental SAT instance generation; industrial benchmarks; Automatic control; Automatic test pattern generation; Benchmark testing; Circuit faults; Circuit testing; Computer science; Design automation; Production; Tellurium; Test pattern generators;
fLanguage
English
Publisher
ieee
Conference_Titel
Design and Diagnostics of Electronic Circuits and Systems, 2008. DDECS 2008. 11th IEEE Workshop on
Conference_Location
Bratislava
Print_ISBN
978-1-4244-2276-0
Electronic_ISBN
978-1-4244-2277-7
Type
conf
DOI
10.1109/DDECS.2008.4538759
Filename
4538759
Link To Document