CAD tool autogeneration of VHDL FFT for FPGA/ASIC implementation

Hand-coding Fast Fourier Transforms (FFTs) in Hardware Description Language (HDL) is time consuming and prone to errors. Proprietary IP cores are available, however they are closed-source and unviewable. The open-source FFT generator SPIRAL is available, however it only produces parallel arithmetic solutions and thus limits the maximum FFT size that will fit in available Field Programmable Gate Arrays (FPGAs). An autogenerator of VHDL FFTs is described that takes a set of FFT parameters and generates an FFT component with feedback of occupied slices, maximum frequency, and dynamic range performance. Both parallel arithmetic and serial-parallel butterfly architectures can be generated where serial-parallel allows larger sized FFTs to fit inside available FPGA parts. Emphasis is placed on large sized serial-parallel FFTs and portability to Application-Specific Integrated Circuits (ASICs) using Cadence Encounter. Serial-parallel FFT pipeline control and FPGA hardware reduction are also investigated.