A Dual-Threaded Architecture for Interval Arithmetic Coprocessor with Shared Floating Point Units

This paper presents a new type of coprocessor architecture suited for both conventional floating point and interval arithmetic. The coprocessor is composed of two logical processors (LP). The floating point units are shared between these two LPs in order to reduce the area overhead. Some functional units implement two or more operations (for example the multiply-add fused (MAF) unit can be used for addition, multiplication or multiply-add fused). The set of functional units can thus help reduce the number of structural hazards and increase the resource utilization (for example, if addition occurs on both LPs, one can be executed on the adder, while the other on the MAF). In order to further reduce the data and structural hazards a scheduler for this architecture is also proposed.