Title :
Multiplexer-based binary incrementer/decrementers
Author :
Bi, Shaoqiang ; Wang, Wei ; Al-Khalili, Asim
Author_Institution :
Dept. of Electr. & Comput. Eng., Concordia Univ., Montreal, Que., Canada
Abstract :
In this paper, novel multiplexer (MUX)-based incrementer/decrementers are proposed. The proposed designs are more efficient in terms of speed and hardware complexity compared to the adder-based ones for both signed and unsigned cases. A FPGA implementation comparison shows that the proposed design reduces both area and delay close to 40%. The power consumed by the MUX-based design is almost 35% less than that of the carry propagation adder (CPA)-based design.
Keywords :
adders; field programmable gate arrays; logic design; FPGA implementation; MUX-based design; adders; field programmable gate arrays; integrated logic circuits; multiplexer-based binary decrementers; multiplexer-based binary incrementers; Adders; Algorithm design and analysis; Bismuth; Circuits; Delay; Digital systems; Field programmable gate arrays; Hardware; Microcontrollers; Multiplexing;
Conference_Titel :
IEEE-NEWCAS Conference, 2005. The 3rd International
Print_ISBN :
0-7803-8934-4
DOI :
10.1109/NEWCAS.2005.1496662
