DocumentCode
1723545
Title
Design and Modeling of ADPLL with sliding-window for wide range frequency tracking
Author
Shan, Chuan ; Galayko, Dimitri ; Anceau, François
Author_Institution
LIP6, UPMC Sorbonne Univ., Paris, France
fYear
2012
Firstpage
269
Lastpage
272
Abstract
An architecture of All-Digital Phase-Locked Loop (ADPLL) with sliding window for wide range frequency tracking is proposed to reduce energy consumption and to accelerate convergence. A synthesizable VHDL model is created for this circuit. Simulation and syntheses results demonstrate high performance of the new architecture.
Keywords
circuit simulation; convergence; hardware description languages; phase locked loops; power consumption; ADPLL design; ADPLL modeling; all-digital phase-locked loop; convergence acceleration; energy consumption reduction; sliding window; synthesizable VHDL model; wide range frequency tracking; Clocks; Computer architecture; Indexes; Phase frequency detector; Phase locked loops; Power demand; Registers;
fLanguage
English
Publisher
ieee
Conference_Titel
New Circuits and Systems Conference (NEWCAS), 2012 IEEE 10th International
Conference_Location
Montreal, QC
Print_ISBN
978-1-4673-0857-1
Electronic_ISBN
978-1-4673-0858-8
Type
conf
DOI
10.1109/NEWCAS.2012.6329008
Filename
6329008
Link To Document