Title :
A digital front-end of 16-bit audio delta-sigma DAC with improved CSE method and novel DWA
Author :
Zhao, Jinchen ; Wu, Xiaobo ; Zhao, Menglian
Author_Institution :
Inst. of VLSI Design, Zhejiang Univ., Hangzhou, China
Abstract :
To achieve area-efficiency and high SNR, a novel digital front-end of a 16-bit audio DAC including a 4-stage interpolator and a 3rd-order delta-sigma (ΣΔ) modulator is proposed. An improved common subexpression elimination (CSE) method is used for implementing the interpolator to save the hardware overhead. And a novel data weighted averaging (DWA) technique named as dual cycle shifted DWA is applied to the 4-bit ΣΔ modulator to reduce the mismatch errors without introducing signal-dependent tones. Implemented in a standard 0.18-μm 1P6M LOGIC salicide process, the proposed design achieves a peak SNR of 103.9-dB and a DR of 104.3-dB, which proves that the proposed work achieves the design goal well.
Keywords :
delta-sigma modulation; interpolation; ΣΔ modulator; 3rd-order delta-sigma modulator; 4-stage interpolator; CSE method; SNR; area-efficiency; audio delta-sigma DAC; data weighted averaging technique; digital front-end; digital-to-analog converters; dual cycle shifted DWA; hardware overhead; improved common subexpression elimination method; mismatch error reduction; signal-to-noise ratio; size 0.18 mum; standard LOGIC salicide process; word length 16 bit; word length 4 bit; Adders; Cascading style sheets; Filtering algorithms; Finite impulse response filter; Hardware; Modulation; Signal to noise ratio;
Conference_Titel :
New Circuits and Systems Conference (NEWCAS), 2012 IEEE 10th International
Conference_Location :
Montreal, QC
Print_ISBN :
978-1-4673-0857-1
Electronic_ISBN :
978-1-4673-0858-8
DOI :
10.1109/NEWCAS.2012.6329009
