DocumentCode
1723616
Title
Low-Voltage Low-Power Highly Linear Down-Sampling Mixer in 65nm Digital CMOS Technology
Author
Schweiger, Kurt ; Zimmermann, Horst
Author_Institution
Inst. of Electr. Meas. & Circuit Design, Vienna Univ. of Technol., Vienna
fYear
2008
Firstpage
1
Lastpage
4
Abstract
A highly linear down-conversion mixer in a 65 nm digital CMOS technology is presented. The mixer was fabricated in a tripple-well process which allows to use the bulk of NMOS transistors as inputs. In contrary to other works not the gate but the bulk connector is used for the input signal. A high IIP3 of +18 dBm was achieved with a power consumption of only 0.67 mW from a 1.2 V supply voltage. The mixer has a measured ldB compression point of +7 dBm. The input signal bandwidth lies beyond 2 GHz.
Keywords
CMOS digital integrated circuits; MOSFET; mixers (circuits); NMOS transistors; digital CMOS; linear down-conversion mixer; linear down-sampling mixer; power 0.67 mW; size 65 nm; tripple-well process; voltage 1.2 V; CMOS digital integrated circuits; CMOS technology; Circuit synthesis; Connectors; Energy consumption; MOSFETs; Mobile communication; Radio frequency; Transceivers; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Design and Diagnostics of Electronic Circuits and Systems, 2008. DDECS 2008. 11th IEEE Workshop on
Conference_Location
Bratislava
Print_ISBN
978-1-4244-2276-0
Electronic_ISBN
978-1-4244-2277-7
Type
conf
DOI
10.1109/DDECS.2008.4538780
Filename
4538780
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