Ultra low leakage structures for logic circuits using symmetric and asymmetric FinFETs

In this paper, FinFET devices are analyzed with emphasis on sub-threshold leakage current control. This is achieved through proper biasing of the back gate, and through use of asymmetric work functions for the four terminal FinFET devices. We are also examining various transistor configurations and circuit topologies for logic gates using both symmetric and asymmetric work function transistors. Based on extensive characterization data, the logic gates using symmetric devices with one additional supply voltage have the best tradeoff between leakage current and performance. However, with asymmetric devices the leakage current drops by an average of 95% with degradation in delay of 8%. For a carry generation complex gate, our configuration, using symmetric devices, both leakage current and delay are improved by 35% and 47% respectively compared to results in the literature. Using asymmetric devices without additional supply achieves average improvements in leakage and delay of 81% and 5% respectively. All simulations are based on 25nm FinFET technology using the University of Florida UFDG model.