• DocumentCode
    1724460
  • Title

    Software-Based Self-Test Strategy for Data Cache Memories Embedded in SoCs

  • Author

    Perez, W.J. ; Medina, J. Velasco ; Ravotto, D. ; Sanchez, E. ; Reorda, M. Sonza

  • Author_Institution
    Grupo de Bionanoelectronica, Univ. del Valle, Cali
  • fYear
    2008
  • Firstpage
    1
  • Lastpage
    6
  • Abstract
    Testing SoC is a challenging task, especially when addressing complex and high- frequency devices. Among the different techniques that can be exploited, software-based selft-test (SBST) emerged as an effective solution, due some advantages it provides (no HW changes, at- speed testing, re-usability); however, the method requires effective techniques for generating suitable test programs. In this paper we face the issue of generating programs to test data caches (in particular their control part): a method is proposed, and some experimental results are provided to assess its effectiveness.
  • Keywords
    automatic programming; automatic testing; cache storage; integrated circuit testing; microprocessor chips; system-on-chip; data cache memories; microprocessor testing; program generation; software-based self-test strategy; system-on-chip testing; test programs; Automatic testing; Built-in self-test; Cache memory; Circuit testing; Costs; Integrated circuit testing; Manufacturing processes; Microprocessors; Software testing; System testing; Cache memories; Microprocessor testing; System-on-Chip testing;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Design and Diagnostics of Electronic Circuits and Systems, 2008. DDECS 2008. 11th IEEE Workshop on
  • Conference_Location
    Bratislava
  • Print_ISBN
    978-1-4244-2276-0
  • Electronic_ISBN
    978-1-4244-2277-7
  • Type

    conf

  • DOI
    10.1109/DDECS.2008.4538813
  • Filename
    4538813