A 6-bit 2GSPS interpolated flash type CMOS A/D converter with a buffered DC reference and one-zero detecting encoder

Author

Park, Yujin ; Hwang, Sanghoon ; Song, Minkyu

Author_Institution

Dept. of Semicond. Sci., Dongguk Univ., Seoul, South Korea

fYear

2005

Firstpage

51

Lastpage

54

Abstract

In this paper, CMOS analog-to-digital converter (ADC) with a 6bits 2GSPS at 1.8V is described. The architecture of the proposed ADC is based on a flash type ADC with interpolation technique to obtain a high-speed operation. In order to overcome the problems of high speed operation, a circuit to reduce the reference fluctuation, a high speed track-and-hold (T/H), a novel one-zero detecting encoder, and a buffered reference for the improvement of SNR are proposed. The fabricated chip with 0.18μm CMOS occupies an area of 977μm × 1040μm and consumes 145mW at 1.8V power supply. The measured SNDR is about 34.55dB and DNL is within 0.5LSB, when the sampling frequency is 2GHz.

Keywords

CMOS integrated circuits; analogue-digital conversion; detector circuits; high-speed integrated circuits; interpolation; reference circuits; sample and hold circuits; 0.18 micron; 1.8 V; 145 mW; 2 GHz; 6 bit; CMOS A/D converter; CMOS analog-to-digital converter; buffered DC reference; flash type A/D converter; high speed track-and-hold; interpolation technique; one-zero detecting encoder; Analog-digital conversion; Circuits; Clocks; Error correction codes; Fluctuations; Frequency; Interpolation; Latches; Logic testing; Sampling methods;

fLanguage

English

Publisher

ieee

Conference_Titel

IEEE-NEWCAS Conference, 2005. The 3rd International

Print_ISBN

0-7803-8934-4

Type

conf

DOI

10.1109/NEWCAS.2005.1496704

Filename

1496704