Title :
45nm Yield model optimization
Author :
Walsh, Brian L. ; Colt, John, Jr. ; Poindexter, Daniel ; Joseph, Thomas
Author_Institution :
IBM Syst. & Technol. Group, Hopewell Junction, NY, USA
Abstract :
Elements of a yield model combining multiple input metrics will be reviewed. This model has been applied to multiple products across 65nm and 45nm SOI technology nodes. It provides long term yield metrics as well as yield diagnostics. Focus will be on the addition of After Develop Inspection (ADI) yield metrics into an existing framework which incorporates high resolution defect scans (PLY) and scribe kerf electrical test data.
Keywords :
circuit optimisation; inspection; integrated circuit yield; microprocessor chips; silicon-on-insulator; SOI technology nodes; after develop inspection; high resolution defect scans; kerf electrical test data; multiple products; yield diagnostics; yield model optimization; Correlation; Data models; Inspection; Measurement; Predictive models; Random access memory; Semiconductor device modeling; Yield; Yield Modeling;
Conference_Titel :
Advanced Semiconductor Manufacturing Conference (ASMC), 2011 22nd Annual IEEE/SEMI
Conference_Location :
Saratoga Springs, NY
Print_ISBN :
978-1-61284-408-4
Electronic_ISBN :
1078-8743
DOI :
10.1109/ASMC.2011.5898162
