Application of CGS stress metrology to advanced process control & monitoring

The improvement of device performance associated with the intentional manipulation of stresses on the transistor scale is an integral part of device fabrication at advanced technology nodes. However, comparatively little attention is given to stress management at within-die and within-wafer length scales. Process variations that occur on these longer length scales can induce significant within-wafer stress variations. In turn, the die-to-die, wafer-to-wafer and lot-to-lot stress variations may have significant impact on device performance and yield. This paper describes the use of the CGS (Coherent Gradient Sensing) stress metrology to characterize the detailed within-wafer and wafer-to-wafer stress variations. The CGS stress maps consist of more than 700,000 data points, enabling new potential applications for stress metrology. Case studies are presented that summarize the use of the CGS data to reveal correlations between stress variations and device performance, lithographic overlay and tool matching.