IP caching for terabit speed routers

Author

Talbot, Bryan ; Sherwood, Timothy ; Lin, Bill

Author_Institution

California Univ., San Diego, La Jolla, CA, USA

Volume

2

fYear

1999

fDate

6/21/1905 12:00:00 AM

Firstpage

1565

Abstract

As network speeds continue to grow, current methods of translating destination IP addresses to output port numbers during routing become inadequately slow. Even though this lookup is often performed in hardware, it may still be limited by DRAM access latencies. We present a method of speeding up access to DRAM based lookup mechanisms by more than a factor of 10 using CPU style memory caches. Real IP router traces taken from several sites are used to validate the caching scheme over a variety of parameters as well as used to study IP address properties that may affect caching performance

Keywords

DRAM chips; cache storage; table lookup; telecommunication network routing; transport protocols; CPU style memory caches; DRAM access latencies; DRAM based lookup mechanisms; IP address properties; IP caching; IP lookup performance; IP router traces; destination IP address translation; lookup; network speeds; output port numbers; terabit speed routers; Delay; Hardware; High-speed networks; Histograms; Random access memory; Routing; Table lookup; Timing; Transceivers;

fLanguage

English

Publisher

ieee

Conference_Titel

Global Telecommunications Conference, 1999. GLOBECOM '99

Conference_Location

Rio de Janeireo

Print_ISBN

0-7803-5796-5

Type

conf

DOI

10.1109/GLOCOM.1999.830043

Filename

830043