Title :
Suppression of NBTI-induced VMIN shifts using hafnium doping to gate poly/SiON interface and optimized NiPt process for 40nm node SRAM cell
Author :
Kitamura, Y. ; Sanuki, T. ; Matsuo, K. ; Shimizu, T. ; Ohta, A. ; Arayashiki, Y. ; Fukui, H. ; Hoshino, T. ; Ueki, Y. ; Yasumoto, A. ; Yoshimura, H. ; Asami, T. ; Oyamatsu, H.
Author_Institution :
Syst. LSI Div., Toshiba Corp., Oita, Japan
Abstract :
Hafnium introduction to poly/SiON interface has been found effective to suppress the increase of minimum operating voltage (VMIN) caused by NBTI-induced VT shift in 40nm node low power SRAM. In addition, the distribution tail of N+ node junction leakage current has been identified as enhancing VMIN failure due to NBTI, and has been improved by optimizing NiPt silicide process. Finally operation of 32Mbit 0.24μm2 low power SRAM with VMIN less than 0.9V has been demonstrated.
Keywords :
SRAM chips; leakage currents; semiconductor doping; N+ node junction leakage current; NBTI; SRAM cell; hafnium doping; Doping; Hafnium; Junctions; MOS devices; Random access memory; Silicides; Stress;
Conference_Titel :
VLSI Technology (VLSIT), 2010 Symposium on
Conference_Location :
Honolulu
Print_ISBN :
978-1-4244-5451-8
Electronic_ISBN :
978-1-4244-5450-1
DOI :
10.1109/VLSIT.2010.5556132
