Anti-ESD impacts on 60-V P-channel LDMOS devices as none-ODs zone inserting in the bulk region

For the reliability considerations, a 60-V power p-channel LDMOS transistor co-designed with none-OD zone in the bulk end by a 0.25-μm process will be evaluated in this paper. From the experimental data found that as the none-OD zones inserting, meanwhile the none-OD zone percentage was increased, the anti-ESD capability will be strengthened too, i.e. its I_t2 value is improved by using this manner. Nevertheless, as the none-OD zone ratio increased, the trigger voltage (V_t1) results of these samples are not changed so much, and all of the variation is in a range of 1 to 2-V. On the other hand, the on-resistance (R_on) result will be decreased, which can be considered as more even conduction. Eventually, from the TLP testing data, we can find that the anti-ESD capability (I_t2 value) upgraded nearly 15.4%, and on-resistance (R_on) value decreased nearly 8.6% as compared with the reference sample.