High speed ADCs dedicated for wideband wireless receivers

In this paper the authors presented and discussed the design of different architectures of high-speed analog-to-digital converters (ADCs) dedicated for wideband wireless receivers such as software-defined radio systems. The interest of the authors concerns three different architectures: a pipelined 10-bit, 50 MS/s, a Flash 6-bit, 1-GS/s, and a band-pass sigma-delta 6-bit, 2-GS/s. A first version of the pipelined ADC and the Flash ADC was fabricated. As part of the sigma-delta ADC, a resonator operating at 2-GHz was fabricated. In addition to the design of these ADCs, a PCB card that supports these ADCs within a wireless receiver prototype was designed and tested. The ADCs technology of fabrication is the CMOS 0.18 μm for the pipelined and the flash, and the CMOS 0.13 μm for the band-pass sigma-delta.