Title :
High yield sub-0.1µm2 6T-SRAM cells, featuring high-k/metal-gate finfet devices, double gate patterning, a novel fin etch strategy, full-field EUV lithography and optimized junction design & layout
Author :
Horiguchi, N. ; Demuynck, S. ; Ercken, M. ; Locorotondo, S. ; Lazzarino, F. ; Altamirano, E. ; Huffman, C. ; Brus, S. ; Demand, M. ; Struyf, H. ; De Backer, J. ; Hermans, J. ; Delvaux, C. ; Vandeweyer, T. ; Baerts, C. ; Mannaert, G. ; Truffert, V. ; Verlu
Author_Institution :
IMEC, Leuven, Belgium
Abstract :
We report high yield sub-0.1μm2 SRAM cells using high-k/metal gate FinFET devices. Key features are (1) novel fin patterning strategy, (2) double gate patterning (3) new SRAM cell layout and (4) EUV lithography and robust etch/fill/CMP for contact/metal 1.0.099μm2 FinFET 6T-SRAM cells show good yield. And smaller cells (0.089μm2) are functional. Further yield improvement is possible by junction optimization using extension less junction approach and further cell layout optimization.
Keywords :
MOSFET; SRAM chips; chemical mechanical polishing; circuit optimisation; etching; high-k dielectric thin films; integrated circuit layout; ultraviolet lithography; SRAM cell layout optimisation; double gate patterning; extension less junction approach; fin etch strategy; fin patterning strategy; full-field EUV lithography; high yield FinFET 6T-SRAM cells; high-k-metal-gate FinFET devices; optimized junction design; robust etch-fill-CMP; FinFETs; Junctions; Layout; Lithography; Logic gates; Optimization; Random access memory;
Conference_Titel :
VLSI Technology (VLSIT), 2010 Symposium on
Conference_Location :
Honolulu
Print_ISBN :
978-1-4244-5451-8
Electronic_ISBN :
978-1-4244-5450-1
DOI :
10.1109/VLSIT.2010.5556133
