Title :
A 0.063 µm2 FinFET SRAM cell demonstration with conventional lithography using a novel integration scheme with aggressively scaled fin and gate pitch
Author :
Basker, V.S. ; Standaert, T. ; Kawasaki, H. ; Yeh, C.-C. ; Maitra, K. ; Yamashita, T. ; Faltermeier, J. ; Adhikari, H. ; Jagannathan, H. ; Wang, J. ; Sunamura, H. ; Kanakasabapathy, S. ; Schmitz, S. ; Cummings, J. ; Inada, A. ; Lin, C.H. ; Kulkarni, P. ;
Author_Institution :
IBM Res., Albany Nano Tech, Albany, NY, USA
Abstract :
We demonstrate the smallest FinFET SRAM cell size of 0.063 μm2 reported to date using optical lithography. The cell is fabricated with contacted gate pitch (CPP) scaled to 80 nm and fin pitch scaled to 40 nm for the first time using a state-of-the-art 300 mm tool set. A unique patterning scheme featuring double-expose, double-etch (DE2) sidewall image transfer (SIT) process is used for fin formation. This scheme also forms differential fin pitch in the SRAM cells, where epitaxial films are used to merge only the tight pitch devices. The epitaxial films are also used for conformal doping of the devices, which reduces the external resistance significantly. Other features include gate-first metal gate stacks and transistors with 25 nm gate lengths with excellent short channel control.
Keywords :
MOSFET; SRAM chips; nanopatterning; photolithography; semiconductor doping; FinFET SRAM cell demonstration; conformal doping; contacted gate pitch; differential fin pitch; double-etch sidewall image transfer process; double-expose sidewall image transfer process; epitaxial films; fin formation; gate-first metal gate stacks; integration scheme; optical lithography; patterning scheme; short channel control; size 25 nm; size 40 nm; size 80 nm; transistors; Doping; Epitaxial growth; FinFETs; Lithography; Logic gates; Random access memory;
Conference_Titel :
VLSI Technology (VLSIT), 2010 Symposium on
Conference_Location :
Honolulu
Print_ISBN :
978-1-4244-5451-8
Electronic_ISBN :
978-1-4244-5450-1
DOI :
10.1109/VLSIT.2010.5556135
