Title :
Feasibility of a digital design flow of an asynchronous BCJR/MAP convolutional channel decoder
Author :
Perta, Kristofer ; Tepe, Kemal E.
Author_Institution :
Res. Centre for Integrated Microsystems, Windsor Univ., Ont., Canada
Abstract :
The current technology in the design of BCJR or MAP decoders utilizes standard electronic design and automation (EDA) tools in the synchronous paradigm. The BCJR/MAP decoder has gained large scale importance in convolutional coding, especially with its importance in turbo codes. This paper examines the feasibility and benefits of an asynchronous design of a BCJR/MAP decoder. A comparison against other gate level decoders is examined and promising results are shown.
Keywords :
asynchronous circuits; channel coding; convolutional codes; electronic design automation; logic design; turbo codes; BCJR decoder; MAP decoder; asynchronous decoder; convolutional channel decoder; convolutional coding; digital design flow; electronic design automation tools; gate level decoders; turbo codes; Asynchronous circuits; Circuit noise; Circuit synthesis; Clocks; Convolutional codes; Decoding; Noise reduction; Synchronization; Turbo codes; Very large scale integration;
Conference_Titel :
IEEE-NEWCAS Conference, 2005. The 3rd International
Print_ISBN :
0-7803-8934-4
DOI :
10.1109/NEWCAS.2005.1496735
