A programmable DSP core for baseband processing

A programmable baseband processor architecture is presented. The architecture is based on a specialized DSP processor core and a number accelerators connected via a configurable network. The focus of this paper is the DSP core itself. A novel type of instructions operating on vectors of complex data is used. Implementation of a demonstrator chip and firmware for wireless LAN applications has proven the instruction set to be very efficient, resulting in low program memory cost and moderate clock frequency requirements. The architecture also minimizes data memory size and accesses, which together with a high degree of hardware reuse results in very low silicon cost for multi-standard baseband processors.