A new topology for power control of high efficiency class-E power amplifier

Author

Tabrizi, Mohammad Moghaddam ; Masoumi, Nasser ; Aghnout, Soraya

Author_Institution

Dept. of Electr. & Comput. Eng., Tehran Univ., Iran

fYear

2005

Firstpage

139

Lastpage

142

Abstract

In this paper a new methodology to improve overall efficiency of class E power amplifier is proposed. Power amplifiers are designed to have the maximum efficiency at its highest output power but the efficiency decreases as the output power is reduced. To have more battery life and blocking interference, output power must be controlled due to the distance between the transmitter and the receiver. This new methodology uses optimized circuit topology in power control unit to have small drop in efficiency at low output power. Proposed circuit is simulated with Hspice in 0.25μm CMOS technology and ADS lumped model of spiral inductors is used. The results show that the efficiency drop is about 40% when power amplifier is work with its 10% of output power.

Keywords

CMOS integrated circuits; circuit optimisation; network topology; power amplifiers; power control; 0.25 micron; ADS lumped model; CMOS technology; blocking interference; circuit topology optimization; class-E power amplifier; power control; receiver; spiral inductors; transmitter; Batteries; CMOS technology; High power amplifiers; Interference; Optimization methods; Power amplifiers; Power control; Power generation; Topology; Transmitters;

fLanguage

English

Publisher

ieee

Conference_Titel

IEEE-NEWCAS Conference, 2005. The 3rd International

Print_ISBN

0-7803-8934-4

Type

conf

DOI

10.1109/NEWCAS.2005.1496744

Filename

1496744