DocumentCode :
1725687
Title :
Lithography cost savings through resist reduction and monitoring program
Author :
Couteau, Terri ; Lindauer, Scott ; Stewart, Chris ; Braggin, Jennifer ; Bjornberg, Brent
Author_Institution :
Spansion, Inc., Austin, TX, USA
fYear :
2011
Firstpage :
1
Lastpage :
4
Abstract :
Photolithography has been one of the primary processes driving semiconductor advances for the past few decades. In order to make faster, more reliable devices, designers drive circuit scaling to its limits. Equipment and material suppliers must create products to meet the throughput and lithographic performance standards required of advanced devices. Track equipment performance and process architecture have improved to meet throughput considerations, and therefore the cost of lithography tracks has remained relatively constant and few equipment changes are remaining which will drastically reduce the cost of lithography. On the other hand, the cost of photolithography materials has drastically increased due to the complexity of the chemistries required to resolve shrinking critical dimensions. In addition, new technology nodes have often required additional processing layers, adding to the high cost of materials in the lithography process. These increased costs are directly delivered to the wafer for processes where high volumes of chemical or multiple layers are needed to properly coat a wafer for further processing. By fine tuning the coating process, a track equipment engineer can reduce resist cost per wafer by reducing the volume dispensed on the wafer. While reducing the resist volume to extremely low levels is attractive, it can also introduce risks into the coating process. Any interruption in the low volume dispense can cause a poor coating or no-coat situation, thus creating a wafer that requires rework or scrap. If the event is detected at the point of dispense, the wafer can be reworked. If the wafer escapes undetected until a post-lithography metrology step, it must be scrapped. This paper evaluates the cost benefits of utilizing an advanced dispense system, such as the IntelliGen® Mini, made by Entegris, Inc., combined with an every-wafer point-of-dispense monitoring strategy. This paper will discuss the means to reduce resist dispens- - e volumes by up to 60% and the ability to track every dispense, decreasing overall scrap and the need for some routine metrology. In addition, the authors will show a return-on-investment summary for undertaking such a project.
Keywords :
coating techniques; cost reduction; integrated circuit manufacture; investment; photolithography; Entegris, Inc.; IntelliGen®; coating process; cost savings; drive circuit scaling; lithographic performance; lithography process; monitoring program; photolithography; point-of-dispense monitoring strategy; return-on- investment; semiconductor; track equipment engineer; wafer; Coatings; Inspection; Lithography; Metrology; Monitoring; Resists; photo dispense; photolithography; return on investment;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Advanced Semiconductor Manufacturing Conference (ASMC), 2011 22nd Annual IEEE/SEMI
Conference_Location :
Saratoga Springs, NY
ISSN :
1078-8743
Print_ISBN :
978-1-61284-408-4
Electronic_ISBN :
1078-8743
Type :
conf
DOI :
10.1109/ASMC.2011.5898209
Filename :
5898209
Link To Document :
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