VLSI Architecture of a 4Ã\x974 MIMO-OFDM Transceiver for over 1-Gbps Data Transmission

This paper presents a VLSI architecture of a 4 times 4 MIMO-OFDM transceiver for over 1-Gbps data transmission in forthcoming wireless LAN systems. The IEEE802.11n draft provides date rates of up to 600 Mbps. The IEEE802.11 VHT Study Group considers a signal bandwidth of more than 80 MHz to achieve 1-Gbps throughput in MAC layer. The presented architecture focuses on the VLSI implementation of these wireless specifications and realizes real-time processing in a 4 times 4 MIMO-OFDM configuration, where real-time MIMO detection is discussed as a technical design issue. The proposed MIMO detector drastically reduces processing latency in MIMO detection while the conventional designs suffer from the increasing latency depending on OFDM subcarriers. The implemented transceiver has 6.6 to 8.7 millions in logic gates and consumes 641 to 960 mW in power dissipation.