Automatically retargetable pre-processor and assembler generation for ASIPs

During design space exploration, alternative CPUs are evaluated for an envisaged SoC, thereby requiring fast CPU models and efficient code generation tools. Candidate CPUs may be general-purpose processors, DSPs, micro-controllers or ASIPs. The ASIP is a particularly challenging alternative: since instruction-set architecture (ISA) tailoring is allowed, an ASIP cannot rely on pre-existent code generation tools. Each target ISA requires a new tool chain. Therefore, an automatically retargetable tool chain is mandatory. This paper focuses on a couple of tools from such a chain: pre-processor and assembler. It proposes robust and efficient techniques allowing retargetability through automatic tool generation from a given target ISA, which is formally described by architecture description language (ADL) constructs. Tool robustness results from formal techniques based on context-free grammars. Tool efficiency evidence is provided by experiments targeting three CPUs: MIPS, PowerPC 405 and PIC 16F84.