DocumentCode
1725789
Title
A Novel Bandwidth Enhancement Technique for Cascode Amplifier
Author
Somvanshi, Sameer ; Yousuf, Junaid
Author_Institution
Dept. of ECE, Indian Inst. of Sci., Banglore
fYear
2008
Firstpage
432
Lastpage
435
Abstract
In this paper, a new technique is presented to increase the bandwidth for a single stage amplifier. Usually, -3 dB bandwidth of single stage amplifier is in few MHz. High output impedance and subsequent capacitive loading decrease the bandwidth of amplifier. The presented technique uses a load which itself acts as bandwidth enhancer. This high speed amplifier is designed on 180 nm CMOS technology, operates at 2.5 V power supply. This amplifier is succeeded by an output buffer to achieve a better linearity, high output swing and required output impedance for matching.
Keywords
CMOS integrated circuits; amplifiers; impedance matching; integrated circuit design; CMOS technology; bandwidth enhancement technique; capacitive loading; impedance matching; power supply; single stage cascode amplifier design; size 180 nm; voltage 2.5 V; Bandwidth; CMOS technology; Capacitors; Electronic mail; Frequency; High power amplifiers; Impedance; Inductors; MOSFET circuits; Topology;
fLanguage
English
Publisher
ieee
Conference_Titel
Communications and Information Technologies, 2008. ISCIT 2008. International Symposium on
Conference_Location
Lao
Print_ISBN
978-1-4244-2335-4
Electronic_ISBN
978-1-4244-2336-1
Type
conf
DOI
10.1109/ISCIT.2008.4700229
Filename
4700229
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