Title :
Data flow approach to self-timed logic in VLSI
Author :
Lau, C.H. ; Renshaw, D. ; Mavor, J.
Author_Institution :
Dept. of Electr. Eng., Edinburgh Univ., UK
Abstract :
The author introduces a data-flow approach to the design of logic circuits in CMOS. A natural consequence of the data-flow model of logic operation is the self-timed behaviour of the resultant logic network. Circuits so designed exhibit correct sequencing behaviour, independent of the delay associated with the interconnection of logic operators. A CMOS implementation of data-flow operators based on differential cascode switch logic is presented. An example of a first-in, first-out (FIFO) memory is used to illustrate the technique.<>
Keywords :
CMOS integrated circuits; VLSI; integrated logic circuits; CMOS implementation; FIFO; VLSI; data-flow model; data-flow operators; differential cascode switch logic; logic circuits; self-timed logic; sequencing behaviour; CMOS logic circuits; Clocks; Control systems; Data flow computing; Delay; Flow graphs; Integrated circuit interconnections; Logic circuits; Switches; Very large scale integration;
Conference_Titel :
Circuits and Systems, 1988., IEEE International Symposium on
Conference_Location :
Espoo, Finland
DOI :
10.1109/ISCAS.1988.14968
