Selector design considerations and requirements for 1 SIR RRAM crossbar array

This work investigates the impact of selector characteristics on the overall 1S1R cell performance. Selector requirements are extracted using parameterized characteristics for an 1Mbit array, taking into account the read/write margins and power consumption constraints. Array sizing simulation results show that the voltage operating range of the selector is important. Selectors with large voltage operation range improve full cell non-linearity, but this comes at the cost of reduced 1S1R read window and the need of high voltage during both read and write operations. Using optimized bias scheme enables a larger design margin for the selector compared to the standard 1/2 or 1/3 bias scheme. The use of lower switching current resistive element also enlarges the selector design range, allowing lower non-linearity and voltage operation range. In case a low switching current resistive element is used, it is the read operation that imposes the minimum selector requirements.