An exploratory study on system-aided DRAM scaling

This paper advocates a system-aided DRAM scaling strategy, where the rationale is to embrace, instead of striving to tackle, the difficulty of storage node aspect ratio (A/R) scaling. In current practice, scaling down of DRAM cell size must be strictly accompanied with proportional scaling up of storage node A/R, in order to maintain the storage node capacitance and hence error-free memory operation. Given the significant difficulty of continuing to scale up storage node A/R, relaxing the strict coupling between DRAM cell size scaling down and storage node A/R scaling up appears to be the natural or even only option. Although it inevitably results in error-prone memory operation, explicitly exposing memory errors to system-level memory controllers is a viable option to ensure data storage integrity and meanwhile keep standard memory interface intact. This leads to a system-aided DRAM scaling paradigm, which conceptually resembles the scaling of NAND flash memory. In this exploratory study, we performed analysis and calculations to estimate error characteristics in the presence of storage node capacitance reduction, and propose a data-dependent error-tolerance approach to reduce the redundancy overhead of system-aided DRAM error mitigation. The results of our cross-layer study show a promising potential of this DRAM scaling paradigm, and we believe that it deserves more thorough and cohesive investigations from the system and circuit/device aspects as a plausible path for future DRAM scaling.