An architectural design for parallel fractal compression

Author

Acken, K.P. ; Kim, H.N. ; Irwin, M.J. ; Owens, R.M.

Author_Institution

Dept. of Comput. Sci. & Eng., Pennsylvania State Univ., University Park, PA, USA

fYear

1996

Firstpage

3

Lastpage

11

Abstract

Fractal image compression has many features that makes it a powerful compression scheme, but it has been mainly restricted to archival storage due to its time consuming encoding algorithm. In this paper, we take a known quad-tree fractal encoding algorithm and design an ASIC parallel image processing array that can encode reasonably sized gray-scale images in real-time. In designing this architecture, we include novel optimizations that result in speed improvements at the algorithmic, architectural, and circuit levels

Keywords

application specific integrated circuits; data compression; encoding; fractals; image coding; image processing; parallel architectures; ASIC parallel image processing; architectural design; archival storage; circuit levels; encoding algorithm; gray-scale images; parallel fractal compression; quad-tree fractal encoding algorithm; speed improvements; Algorithm design and analysis; Broadcasting; Computer science; Fractals; Image coding; Image storage; Multimedia communication; Pixel; Power engineering and energy; Video compression;

fLanguage

English

Publisher

ieee

Conference_Titel

Application Specific Systems, Architectures and Processors, 1996. ASAP 96. Proceedings of International Conference on

Conference_Location

Chicago, IL

ISSN

2160-0511

Print_ISBN

0-8186-7542-X

Type

conf

DOI

10.1109/ASAP.1996.542796

Filename

542796