DocumentCode
172638
Title
High performance triangular barrier engineered NIPIN selector for bipolar RRAM
Author
Meshram, R. ; Das, Biswajit ; Mandapati, R. ; Lashkare, S. ; Deshmukh, S. ; Lodha, Saurabh ; Ganguly, Utsav ; Schulze, J.
Author_Institution
Indian Inst. of Technol. Bombay, Mumbai, India
fYear
2014
fDate
18-21 May 2014
Firstpage
1
Lastpage
4
Abstract
Triangular barrier has been proposed and implemented for the first time in a punch-through diode based selector by dopant profile engineering. Vertical 4F2 diodes have been fabricated on an epitaxial Si stack consists of n+ / i / delta-doped p+ / i / n+ (NIPIN) layers by low temperature (sub-520°C) Si epitaxy. We experimentally demonstrate that while conventional NPN selectors exhibit severe sub-threshold slope degradation at high voltage, NIPIN selectors produce ideal subthreshold slope of ~120mV/decade with negligible degradation. Scaled devices show on-current density of 1-2MA/cm2 below 2V. High on-off current ratio of > 104 is estimated from experiments. The NIPIN shows significant improvements over NPN i.e. sub-2V operation (50% improvement) and non-linearity > 104 (i.e. 2 orders improvement). Perimeter scaling of current due to fringing fields is demonstrated experimentally which improves current density in area scaled devices. Further, the excellent device performance indicates the high quality Si epitaxy grown at sub-520°C that enables low trap density and high in situ dopant activation.
Keywords
current density; elemental semiconductors; epitaxial growth; random-access storage; silicon; NPN selectors; Si; area scaled devices; bipolar RRAM; device performance; dopant profile engineering; epitaxial stack; fringing fields; ideal subthreshold slope; in situ dopant activation; low trap density; on-current density; on-off current ratio; perimeter scaling; punch-through diode based selector; sub-threshold slope degradation; temperature 520 C; triangular barrier engineered NIPIN selector; vertical 4F2 diodes; Arrays; Current density; Degradation; Doping profiles; Epitaxial growth; Performance evaluation; Silicon; bipolar RRAM; delta-doping; low temperature epitaxy; punch-through; selector; silicon;
fLanguage
English
Publisher
ieee
Conference_Titel
Memory Workshop (IMW), 2014 IEEE 6th International
Conference_Location
Taipei
Print_ISBN
978-1-4799-3594-9
Type
conf
DOI
10.1109/IMW.2014.6849388
Filename
6849388
Link To Document