Analyzing single bit failure in SRAM with no visual defects

We present a simulation methodology to analyze single bit fails in SRAMs with no visual defect to account for the failure. Our approach generates the MOS IV curves for all six transistors of the failing bit cell and uses this data to simulate read, write and read-disturb failures. A good agreement with the tester data then establishes the basis for the failure even in the absence of any visual defect(s).