A Novel Sub-20V Power MOSFET with Improved On-Resistance and Threshold Variation

Author

Ng, Jacky C W ; Sin, Johnny K O ; Guan, Lingpeng

Author_Institution

Dept. of Electron. & Comput. Eng., Hong Kong Univ. of Sci. & Technol., Kowloon

fYear

2008

Firstpage

91

Lastpage

94

Abstract

In this paper, a novel planar power MOSFET using ion implantation to form the body and JFET regions is presented. The novel device is compared with conventional planar VDMOS devices. The specific on-resistance is reduced by 32% due to the reduction in JFET resistance. The standard deviation of the threshold voltage is reduced from 36 to 10 mV, because the channel region of the novel device is uniformly doped by using ion implantation. The gate-drain charge density is similar, and there is a 28% reduction in the figure-of-merit. The breakdown and threshold voltages of the novel device are 14 and 0.57 V, respectively.

Keywords

ion implantation; junction gate field effect transistors; power MOSFET; JFET resistance; gate-drain charge density; ion implantation; junction gate field effect transistors; metal-oxide-semiconductor field effect transistors; on-resistance; planar power MOSFET; threshold variation; threshold voltage; voltage 36 mV to 10 mV; Doping; Fabrication; Immune system; Ion implantation; MOSFET circuits; Power MOSFET; Power semiconductor devices; Rapid thermal annealing; Silicon compounds; Threshold voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Power Semiconductor Devices and IC's, 2008. ISPSD '08. 20th International Symposium on

Conference_Location

Orlando, FL

Print_ISBN

978-1-4244-1532-8

Electronic_ISBN

978-1-4244-1533-5

Type

conf

DOI

10.1109/ISPSD.2008.4538905

Filename

4538905