Air-isolated through-wafer interconnects for microsystem applications

This paper reports a through-wafer interconnect structure using air-isolated p/sup ++/ silicon columns suspended by metal beams. The approach minimizes parasitic capacitance and does not require the lightly-doped wafers and DC bias associated with pn-junction isolation. The interconnects are therefore well suited for use in battery-operated microsystems. The through-wafer conductors have a calculated series resistance of approximately 5 /spl Omega/ and a capacitance to the substrate of 10 fF. Including the metal support frame, the area of each feedthrough is 0.01 mm/sup 2/, and using clustered columns, the per-feedthrough area is still smaller.