Title :
Implementation of 85V High Side LDMOS with n-layer in a 0.35um BCD Process
Author :
Ko, Choul-Joo ; Lee, Sang-Yong ; Park, Il-Yong ; Park, Cho-Eung ; Jun, Bon-Keun ; Lee, Yong-Jun ; Kang, Chan-Hee ; Lee, Jae-O ; Kim, Nam-Joo ; Yoo, Kwang-Dong
Author_Institution :
Dongbu Hitek, Bucheon
Abstract :
This paper report 85 V high-side LDMOS which is implemented in a conventional 0.3 5 um BCDMOS process using one additional mask. The process has no thermal budget modification but use simple additional implant step. Also it is completely compatible with the conventional BCDMOS process and has similar performances with 80 V SOI LDMOS.
Keywords :
BIMOS integrated circuits; CMOS integrated circuits; BCDMOS process; LDMOS; size 0.35 mum; voltage 80 V; voltage 85 V; Degradation; Doping; Electric breakdown; Electrodes; Implants; Power semiconductor devices; Protection; Silicon on insulator technology; Substrates; Voltage;
Conference_Titel :
Power Semiconductor Devices and IC's, 2008. ISPSD '08. 20th International Symposium on
Conference_Location :
Orlando, FL
Print_ISBN :
978-1-4244-1532-8
Electronic_ISBN :
978-1-4244-1533-5
DOI :
10.1109/ISPSD.2008.4538908
