Title :
Performance Evaluation of Low Density Parity Check Codes for IEEE 802.11n and Its ASIC Design
Author :
Syafei, W.A. ; Nagao, Yuhei ; Yohena, R. ; Shimajiri, H. ; Yoshida, T. ; Kurosaki, Masayuki ; Sai, Baiko ; Ochi, H.
Author_Institution :
Dept. of Comput. Sci. & Electron., Kyushu Inst. of Technol., Iizuka
Abstract :
In this paper we investigate the performance enhancement due to the implementation of low density parity check (LDPC) codes on IEEE 802.11n system under channel model B TGn and its application specific integrated circuit design. Simulation result shows that LDPC codes gives 6 dB better performance compared to binary convolutional codes. Logic synthesis on 0.13 mum CMOS technology with low-power standard cell library shows that the proposed min-sum algorithm-based LDPC decoder is suitable for portable devices.
Keywords :
CMOS integrated circuits; application specific integrated circuits; logic design; network synthesis; parity check codes; wireless LAN; ASIC design; CMOS technology; IEEE 802.11n system; LDPC code; application specific integrated circuit design; channel model; logic synthesis; low density parity check code; low-power standard cell library; min-sum algorithm; size 0.13 mum; Application specific integrated circuits; CMOS logic circuits; CMOS technology; Circuit simulation; Convolutional codes; Integrated circuit modeling; Integrated circuit synthesis; Logic devices; Parity check codes; Semiconductor device modeling;
Conference_Titel :
Communications and Information Technologies, 2008. ISCIT 2008. International Symposium on
Conference_Location :
Lao
Print_ISBN :
978-1-4244-2335-4
Electronic_ISBN :
978-1-4244-2336-1
DOI :
10.1109/ISCIT.2008.4700264
