• DocumentCode
    1726536
  • Title

    Assembly-stress-mechanism in pad areas on high-k/metal gate transistors

  • Author

    Ota, Yukitoshi ; Itoh, Fumito ; Ishikawa, Kazuhiro ; Hagihara, Kiyomi ; Matsumoto, Takeshi ; Iwase, Teppei ; Itoh, Yutaka ; Hirano, Hiroshige

  • Author_Institution
    Panasonic Corp., Nagaokakyo, Japan
  • fYear
    2010
  • Firstpage
    107
  • Lastpage
    108
  • Abstract
    We reveal the mechanism of assembly stress in pad areas of flip chip package by using our new local stress evaluation technique in μm resolution. The technique is designed to evaluate the characteristic change of high-k/metal gate transistors (Trs) that are arrayed in μm pitch.
  • Keywords
    flip-chip devices; semiconductor device manufacture; transistors; assembly-stress-mechanism; flip chip package; high-k/metal gate transistors; pad areas; Apertures; Assembly; Metals; Silicon; Stress; Substrates; Temperature dependence;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    VLSI Technology (VLSIT), 2010 Symposium on
  • Conference_Location
    Honolulu
  • Print_ISBN
    978-1-4244-5451-8
  • Electronic_ISBN
    978-1-4244-5450-1
  • Type

    conf

  • DOI
    10.1109/VLSIT.2010.5556189
  • Filename
    5556189
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1726536