Title :
A new CMOS circuit representation for timing verification
Author :
Liao, Jiann ; Ni, Lionel M.
Author_Institution :
Dept. of Comput. Sci., Michigan State Univ., East Lansing, MI, USA
Abstract :
A structured logical circuit expression (SLICE) is proposed to unify the representation of restoring logic gate and path transistor logic, which are two major logic styles in CMOS circuit design. The SLICE representation provides a systematic way to describe signal flow in CMOS transistor networks. Timing verification can be easily performed by the SLICE representation due to its natural capacity for path enumeration and critical path analysis. Moreover, signal paths and logic stages of a CMOS circuit can be identified to facilitate efficient timing verification.<>
Keywords :
CMOS integrated circuits; integrated logic circuits; CMOS circuit representation; SLICE representation; critical path analysis; logic stages; path enumeration; path transistor logic; restoring logic gate; signal flow; structured logical circuit expression; timing verification; CMOS logic circuits; Circuit simulation; Circuit synthesis; Logic design; Logic gates; Signal design; Signal processing; Signal restoration; Switches; Timing;
Conference_Titel :
Circuits and Systems, 1988., IEEE International Symposium on
Conference_Location :
Espoo, Finland
DOI :
10.1109/ISCAS.1988.14969
