Impact of thinning and through silicon via proximity on High-k / Metal Gate first CMOS performance

Author

Mercha, A. ; Redolfi, A. ; Stucchi, M. ; Minas, N. ; Van Olmen, J. ; Thangaraju, S. ; Velenis, D. ; Domae, S. ; Yang, Y. ; Katti, G. ; Labie, R. ; Okoro, C. ; Zhao, M. ; Asimakopoulos, P. ; De Wolf, I. ; Chiarella, T. ; Schram, T. ; Rohr, E. ; Van Ammel,

Author_Institution

IMEC, Leuven, Belgium

fYear

2010

Firstpage

109

Lastpage

110

Abstract

3D integration has the potential to alleviate the performance limitations that CMOS scaling is facing provided that it preserves the integrity of both front end and back end devices and constituting materials. The impact of wafer thinning and of the proximity of through silicon via on active devices, back end structures, ring oscillators and mixed signal circuit are reported for the first time for a High-k/Metal Gate first strained CMOS technology with low-k BEOL. The relative stress induced by the STI and the TSV are measured by micro-Raman spectroscopy. The measured impact of the stress on a sensitive DAC circuit is used to define a safe keep out area.

Keywords

CMOS integrated circuits; Raman spectroscopy; digital-analogue conversion; high-k dielectric thin films; integrated circuit interconnections; mixed analogue-digital integrated circuits; three-dimensional integrated circuits; 3D integration; CMOS scaling; DAC circuit; back end structures; high-k metal gate; micro-Raman spectroscopy; mixed signal circuit; relative stress; ring oscillators; through silicon via proximity; wafer thinning; CMOS integrated circuits; Logic gates; MOSFET circuits; Metals; Resistance; Stress; Through-silicon vias;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Technology (VLSIT), 2010 Symposium on

Conference_Location

Honolulu

Print_ISBN

978-1-4244-5451-8

Electronic_ISBN

978-1-4244-5450-1

Type

conf

DOI

10.1109/VLSIT.2010.5556190

Filename

5556190