IP-on-the-fly packet processing mechanism for an ATM/IP integrated switch

We propose a new packet processing mechanism caged IP-on-the-fly for an ATM and IP integrated switch used in IETF classical IP over ATM networks. The proposed mechanism enables ATM-based QOS control for IP traffic as well as wire-speed IP packet forwarding in the switch. One of the attractive features of this mechanism is that IP over ATM multi-layer protocol processing is logically performed in a cell-by-cell manner without packet reassembling, which contributes to the high-speed processing and cost reduction. The necessary processing mechanisms and functional configurations for the proposed mechanism are described