• DocumentCode
    1727172
  • Title

    A low-voltage biasing scheme for aggressively scaled bulk FinFET 1T-DRAM featuring 10s retention at 85°C

  • Author

    Collaert, N. ; Aoulaiche, M. ; De Wachter, B. ; Rakowski, M. ; Redolfi, A. ; Brus, S. ; De Keersgieter, A. ; Horiguchi, N. ; Altimime, L. ; Jurczak, M.

  • Author_Institution
    IMEC, Leuven, Belgium
  • fYear
    2010
  • Firstpage
    161
  • Lastpage
    162
  • Abstract
    Retention times up to 10s at 85°C can be achieved for bulk FinFET 1T-DRAM devices using an optimized biasing scheme which targets the storage of electrons in the fin. The impact of the ground plane doping is investigated and finally the read-out scheme is also demonstrated on SOI FinFET devices.
  • Keywords
    DRAM chips; MOSFET; low-power electronics; readout electronics; semiconductor doping; silicon-on-insulator; SOI FinFET device; bulk FinFET 1T-DRAM device; ground plane doping; low-voltage biasing scheme; optimized biasing scheme; read-out scheme; retention time; temperature 85 C; time 10 s; Doping; Electric potential; FinFETs; Logic gates; Programming; Scalability;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    VLSI Technology (VLSIT), 2010 Symposium on
  • Conference_Location
    Honolulu
  • Print_ISBN
    978-1-4244-5451-8
  • Electronic_ISBN
    978-1-4244-5450-1
  • Type

    conf

  • DOI
    10.1109/VLSIT.2010.5556211
  • Filename
    5556211
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1727172