Title :
Automatic memory failure analysis using an expert system in conjunction with a memory tester/analyzer
Author :
Tsujide, T. ; Hamada, H. ; Lepejian, D. ; Caywood, J.M.
Author_Institution :
NEC Corp., Kawasaki, Kanagawa, Japan
Abstract :
A methodology by which predictions of memory failure are made prior to manufacturing is presented. Based on these predictions and supporting historical data, expert rules are automatically created and used in conjunction with a memory tester/analyzer to determine the underlying physical causes of particular memory device failures. The histogram of the failure causes for a given lot can be plotted and evaluated. Examples of the application of this methodology to the manufacture of 4-Mb DRAMs are given.<>
Keywords :
DRAM chips; circuit reliability; expert systems; failure analysis; integrated circuit testing; DRAMs; device failures; expert rules; expert system; memory tester/analyzer; physical causes; Automatic testing; Capacitors; Expert systems; Failure analysis; Manufacturing; National electric code; Nonvolatile memory; Random access memory; System testing; Volume measurement;
Conference_Titel :
Reliability Physics Symposium, 1993. 31st Annual Proceedings., International
Conference_Location :
Atlanta, GA, USA
Print_ISBN :
0-7803-0782-8
DOI :
10.1109/RELPHY.1993.283326
