Title :
Highly reliable vertical NAND technology with biconcave shaped storage layer and leakage controllable offset structure
Author :
Cho, Won-seok ; Shim, Sun Il ; Jang, Jaehoon ; Cho, Hoo-sung ; You, Byoung-Koan ; Son, Byoung-Keun ; Kim, Ki-hyun ; Shim, Jae-Joo ; Park, Choul-min ; Lim, Jin-soo ; Kim, Kyoung-Hoon ; Chung, De-will ; Lim, Ju-Young ; Moon, Hui-Chang ; Hwang, Sung-min ; Li
Author_Institution :
Flash Core Technol. Lab., Samsung Electron. Co. Ltd., Yongin, South Korea
Abstract :
The performance and reliability of 3-D NAND cells fabricated by TCAT (Terabit Cell Array Transistor) technology have been improved significantly via a damascened metal gates and a controlled offset between BL contact and select transistor. The damascened metal gate providing sufficiently low resistance is achieved by adopting a novel metal process. Highly suppressed disturbance property is achieved by the appropriate offset which reduces the leakage current through the select transistor. It is proved that the TCAT NAND is a manufacturable technology in terms of reliability as well as performance in a channel hole with a diameter of 90nm.
Keywords :
electric resistance; leakage currents; logic gates; semiconductor device reliability; transistors; 3D NAND cells fabrication; BL contact; TCAT NAND; TCAT technology; biconcave shaped storage layer; channel hole; damascened metal gate; disturbance property; leakage controllable offset structure; leakage current; low resistance; manufacturable technology; metal process; reliability; select transistor; size 90 nm; terabit cell array transistor; vertical NAND technology; Flash memory; Leakage current; Logic gates; Resistance; Transistors; Tungsten; 3D; CTF; Flash memory; TCAT; Vertical;
Conference_Titel :
VLSI Technology (VLSIT), 2010 Symposium on
Conference_Location :
Honolulu
Print_ISBN :
978-1-4244-5451-8
Electronic_ISBN :
978-1-4244-5450-1
DOI :
10.1109/VLSIT.2010.5556216
