A sliding scale method to reduce the differential non linearity of a time digitizer

A novel technique for improving the differential nonlinearity (DNL) of an existing time digitizer is presented. Modern subnanosecond time to digital converters that interpolate within a slower clock to achieve a high effective clock rate (and correspondingly small least count) usually exhibit DNL, which is a direct result of imperfections in the interpolation. This can be substantially reduced by applying a sliding scale in the time domain. A comparison of results with and without the sliding scale are presented for a widely used commercial time digitizer.