Author :
Witters, L. ; Takeoka, S. ; Yamaguchi, S. ; Hikavyy, A. ; Shamiryan, D. ; Cho, M. ; Chiarella, T. ; Ragnarsson, L.A. ; Loo, R. ; Kerner, C. ; Crabbe, Y. ; Franco, J. ; Tseng, J. ; Wang, W.E. ; Rohr, E. ; Schram, T. ; Richard, O. ; Bender, H. ; Biesemans,
Abstract :
We report low Vt (Vt,Lg=1μm=±0.26V) high performance CMOS devices with ultra-scaled Tinv down to Tinv~8Å using a gate-first dual Si/SiGe channel low-complexity integration approach. Compared to a dual dielectric cap gate-first integration scheme, the devices fabricated with the novel scheme show for the same high-k/metal gate stack (1) 3Å reduction in nMOS and pMOS Tinv (2) 220mV lower long channel pMOS Vt (3) 21%/12% pMOS/nMOS drive current increase at Ioff=100nA/μm and (4) 50% improvement in long channel pMOS Vt variability. For a fixed Tinv of 12Å, a 4 times higher hole mobility and 350mV increase in NBTI 10years lifetime operating voltage are obtained.
Keywords :
MOS integrated circuits; gate-first dual Si/SiGe channel low-complexity integration approach; gate-first dual channel technology; high performance CMOS devices; hole mobility; lifetime operating voltage; nMOS; pMOS; Annealing; CMOS integrated circuits; Logic gates; MOS devices; Metals; Silicon; Silicon germanium; CMOS; SiGe; dual channel; low EOT; low Vt;
